Many hardware accelerator architectures use DMA units to transfer memory which may be limited by the fixed-width size of the DMA transfer, and automatic loop tilers currently do not take the limitation of these DMA units into account. We present a compiler pass, implemented in MLIR, that uses polyhedral analysis on the memory access patterns in a loop nest and constrain the possible tile sizes based on the DMA chunk width. This allows the compiler to effectively tile loops for these architectures.
Alexandre Singer and Kai-Ting Amy Wang. 2023. Tiling for DMA-Based Hardware Accelerators (WIP). In Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2023). Association for Computing Machinery, New York, NY, USA. 5 pages.
Keywords: Optimizations, Compiler, Tiling, Hardware Accelerators, MLIR, Polyhedral
https://doi.org/10.1145/3589610.3596283There is a growing need for higher level abstractions for device kernels in heterogeneous environments, and the multi-level nature of the MLIR infrastructure perfectly addresses this requirement. As SYCL begins to gain industry adoption for heterogeneous applications and MLIR continues to develop, we present SYCLops: a converter capable of translating SYCL specific LLVM IR to MLIR. This will allow for both target and application specific optimizations within the same framework to exploit opportunities for improvement present at different levels.
Alexandre Singer, Frank Gao, and Kai-Ting Amy Wang. 2022. SYCLops: A SYCL Specific LLVM to MLIR Converter. In International Workshop on OpenCL (IWOCL'22). Association for Computing Machinery, New York, NY, USA. 8 pages.
Keywords: IR Converter, MLIR, Heterogeneous Computing, LLVM, SYCL
https://doi.org/10.1145/3529538.3529992